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O que (quem) é HLT (x86 instruction) - definição

X86 CPU INSTRUCTION WHICH PAUSES EXECUTION

HLT instruction

HLT (x86 instruction)

In the x86 computer architecture, HLT (halt) is an assembly language instruction which halts the central processing unit (CPU) until the next external interrupt is fired. Interrupts are signals sent by hardware devices to the CPU alerting it that an event occurred to which it should react.

https://en.wikipedia.org/wiki/HLT_(x86_instruction)

X86 instruction listings

WIKIMEDIA LIST ARTICLE

X86 instruction set; List of x86 assembly language instructions; List of x86 assembler instructions; X86 instructions; X86 assembly instructions; X86 assembly instruction; ARPL (opcode); ARPL (instruction); MOV (x86 instruction); LES (x86 instruction); JZ (x86 instruction); Fsincos; FSINCOS; FXSAVE; Undocumented instruction (x86 instruction); Undocumented instructions (x86 instruction); Undocumented x86 instruction; Undocumented x86 instructions

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

https://en.wikipedia.org/wiki/X86_instruction_listings

X86

TYPE OF INSTRUCTION SET ARCHITECTURE

80x86; Intel 80x86; 8x86; 80786; X86-16; Intel 80786; Intel x86; IA 32; X-86; X86 pro; X86-based CPU; X86-based system; X86 based; X86 clone; X86 compatible; Intel-based CPU; Intel-based cpu; Intel 16; Intel compatible; Intel-compatible; Intel clone; X86 architecture; Accumulator eXtended; AL register; AH register; AX register; BX register; CX register; DX register; BH register; BL register; CL register; CH register; DH register; DL register; Base pointer; DS register; ES register; SS register; DI register; SI register; FS register; GS register; X86 registers; BP register; EAX register; EBX register; ECX register; EDX register; ESP register; EBP register; ESI register; EDI register; EIP register; RIP register; RFLAGS register; RAX register; RBX register; RCX register; RDX register; RSI register; RDI register; RBP register; RSP register; GDTR register; LDTR register; IDTR register; TR register; IP register; Source index; Destination index; IAPX 86 series; X86 microprocessor

and so cannot be subject to patent claims. The pre-586 subset of the x86 architecture is therefore fully open.

https://en.wikipedia.org/wiki/X86

Wikipédia

HLT (x86 instruction)

In the x86 computer architecture, HLT (halt) is an assembly language instruction which halts the central processing unit (CPU) until the next external interrupt is fired. Interrupts are signals sent by hardware devices to the CPU alerting it that an event occurred to which it should react. For example, hardware timers send interrupts to the CPU at regular intervals.

Most operating systems execute a HLT instruction when there is no immediate work to be done, putting the processor into an idle state. In Windows NT, for example, this instruction is run in the "System Idle Process". On x86 processors, the opcode of HLT is 0xF4.

https://en.wikipedia.org/wiki/HLT (x86 instruction)